Operator
An operator is a logical or mathematical function which takes one or two
values and produces a single result. Operators are built into the syntax of the
language, i.e. you cannot define new operators. Operators can be redefined
(overloaded in VHDL jargon) for any types by writing new functions.
Syntax
{2 operands: Expression Operator Expression}
+ - * / mod rem **
= /= < <= > >=
and or xor nand nor xnor
sll srl sla sra rol ror
&
{1 operand: Operator Expression}
+ - abs not
Where
function ""
See Expression
Rules
/ on integers truncates toward 0.
mod and rem give the remainder on division. A rem B has the sign of A, A
mod B has the sign of B.
A sla B replicates the rightmost bit of A, A sra B replicates the leftmost bit of
A.
A & B yields a vector whose length is the length of A + the length of B, with
the content of A on the left and B on the right.
Things to remember
The default definitions of > >= < <= give unexpected results for vectors of
different lengths, e.g. "000" > "00" !
When the "+" operator is overloaded on type Std_logic_vector, it is usual to
make the width of the result equal to that of the widest operand, with the effect
that the result is truncated, e.g. "1" + "1" = "0" and "111" + "1" = "000".
Synthesis
The operators + - = /= < <= > >= are synthesizable as adders,
subtractors and comparators.
The operators / mod rem ** are not synthesizable in general, but may be
synthesized when used to do masks and shifts or in static expressions (e.g. A
/ 2 means shift right).
See Also
Expression, Function
|